The present invention relates generally to integrated circuits, and more specifically to synchronizing internal clocking signals generated in an integrated circuit with external clocking signals applied to the integrated circuit.
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, xe2x80x9cexternalxe2x80x9d is used to refer to signals and operations outside of the memory device, and xe2x80x9cinternalxe2x80x9d to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), measure controlled delays (MCDs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are nominally coincident and signals that have a desired delay relative to one another. FIG. 1 is a functional block diagram of a conventional SMD 100 that receives an applied clock signal CLK and generates a synchronized clock signal CLKSYNC in response to the CLK signal, the CLKSYNC being synchronized with the CLK signal. The SMD 100 includes an input buffer 102 that receives the CLK and generates a buffered clock signal CLKBUF in response to the CLK signal. The CLKBUF signal has a delay D1 relative to the CLK signal, where D1 corresponds to the inherent propagation delay of the input buffer.
A model delay line 104 receives the CLKBUF signal and generates a forward delay clock signal FDCLK having a model delay D1+D2 relative to the CLKBUF signal. The model delays D1 and D2 simulate the delay D1 introduced by the input buffer 102 and a delay D2 introduced by an output buffer 106 that generates the CLKSYNC signal, as will be explained in more detail below. The FDCLK signal propagates through a forward delay line 108 including a plurality of unit delays 11A-N coupled in series, each unit delay receiving an input signal from the prior unit delay and generating an output signal having a unit delay UD relative to the input signal. Each unit delay 110A-N may, for example, be an AND gate having one input enabled as indicated for the unit delay 110A, with the inverter introducing the unit delay UD corresponding to the propagation delay of the inverter. In the forward delay line 104, the FDCLK signal propagates through the unit delays 110A-N from left to right in FIG. 1, as indicated by the orientation of the inverter in the unit delay 110A. The forward delay line 108 includes a plurality of outputs 112A-N, each output 112A-N being coupled to the output from the corresponding unit delay 110A-N, respectively. As the FDCLK signal propagates through the unit delays 110A-N, when the signal is present on a respective output 112A-N the signal is designated a delayed forward clock signal DFDCLK.
A backward delay line 114 includes a plurality of unit delays 116A-N coupled in series as previously described for the forward delay line 108. Instead of providing the outputs from the unit delays 116A-N as with the forward delay line 108, however, the backward delay line 114 has a plurality of inputs 118A-N, each input being coupled to the input of the corresponding unit delay 116A-N, respectively. Once again, each unit delay 116A-N may be formed by an AND gate having one input coupled to the corresponding input 118A-N. A mirror controller 120 is coupled to the outputs 112A-N of the forward delay line 108 and the inputs 118A-N of the backward delay line 114. In response to rising-edges of the CLKBUF signal, the mirror controller 120 applies the DFDCLK signal from the corresponding unit delay 110A-N in the forward delay line 108 to the input of the corresponding unit delay 116A-N in the backward delay line 114. For example, if the FDCLK signal has propagated to the output of the unit delay 110J, the mirror controller 120 outputs the DFDCLK signal on the output of the unit delay 110J to the input of the unit delay 116J in the backward delay line 114. The unit delays 116A to 116I and 116K to 116N are unaffected. The DFDCLK signal propagates through the corresponding unit delay 116J in the backward delay line 114 and through all unit delays 116I-A to the left of that unit delay, and is output from the backward delay line 114 as a delayed clock signal CLKDEL. Thus, in the backward delay line 114, DFDCLK signal propagates through the unit delays 116A-N from right to left in FIG. 1, as indicated by the orientation of the AND gate in the unit delay 116A. The output buffer 106 receives the CLKDEL signal and generates the CLKSYNC in response to the CLKDEL signal, with the CLKSYNC being delayed by the delay D2 introduced by the output buffer.
The overall operation of the SMD 100 in synchronizing the CLKSYNC signal with the CLK signal will now be described in more detail with reference to FIG. 1 and a signal timing diagram of FIG. 2 illustrating various signals generated by the SMD during operation. In the example of FIG. 2, an initial rising-edge of the CLK signal occurs at a time T0. In response to the rising-edge of the CLK signal at the time T0, the input buffer 102 drives the CLKBUF signal high the delay D1 later at a time T1, with this initial rising-edge of the CLKBUF signal being designated the N edge of the CLKBUF signal. In response to the rising-edge transition of the CLKBUF signal at the time T1, the mode delay line 104 drives the FDCLK signal high the model delay D1+D2 later at a time T2. The FDCLK signal thereafter propagates through the unit delays 110A-N in the forward delay line 108 until a next rising-edge N+1 of the CLKBUF signal is applied to the mirror controller 120 at a time T3. At the time T3 , the forward delay line 108 has delayed the FDCLK signal by a forward delay FD that equals TCKxe2x88x92(D1+D2) where TCK is the period of the CLK signal. This is true because, as illustrated in FIG. 2, the next rising-edge of the CLKBUF signal occurs TCKxe2x88x92(D1+D2) after the initial rising-edge of the FDCLK signal at the time T2.
In response to the rising-edge of the CLKBUF signal at the time T3 , the mirror controller 120 applies the FDCLK signal from the output of the appropriate unit delay 110A-N in the forward delay line 108 to the corresponding input 118A-N of the backward delay line 114. For example, assume that the delay TCKxe2x88x92(D1+D2) equals eleven unit delays UD so that the mirror controller 120 receives the DFDCLK signal from the output 112K of the unit delay 110K in the forward delay line 108. In this situation, the mirror controller 120 applies the DFDCLK signal to the input 118K of the unit delay 116K in the backward delay line 114. This is illustrated in FIG. 2 as a rising-edge of the DFDCLK signal at the time T3.
The DFDCLK signal thereafter propagates through the appropriate unit delays 116J-A in the backward delay line 114, and at a time T4 the backward delay line 114 drives the CLKDEL signal high in response to the applied DFDCLK signal. At the time T4, the backward delay line 114 has delayed the DFDCLK signal by a backward delay BD that equals TCKxe2x88x92(D1+D2) which equals the forward delay FD of the forward delay line 108. This is true because the DFDCLK signal propagates through the same number of unit delays 116A-N in the backward delay line 114 as did the FDCLK signal to the unit delays 110A-N in the forward delay line 108, as will be appreciated by those skilled in the art. The total delay of the CLKDEL signal at the time T4 equals D1+D1+D2+TCKxe2x88x92(D1+D2)+TCKxe2x88x92(D1+D2), which equals 2TCKxe2x88x92D2. Thus, the rising-edge of the CLKDEL signal at the time T4 occurs the delay D2 of the output buffer 106 before a next rising-edge of the CLK signal at a time T5. In response to the CLKDEL signal at the time T4, the output buffer 106 drives the CLKSYNC signal high at the time T5 and in synchronism with the rising-edge of the CLK signal. In this way, the SMD 100 generates the CLKSYNC signal having rising-edges that are synchronized with the rising-edges of the CLK signal.
In the SMD 100, although the input buffer 102 and output buffer 106 are illustrated as single components, each represents all components and the associated delays between the input and output of the SMD 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the model delay line 104, and the output buffer 106 represents the delay D2 of all components between the output of the backward delay line 114 and an output at which the CLKSYNC signal is developed, as will be appreciated by those skilled in the art.
In SMD 100, the forward and backward delay lines 108, 114 each include the same number of unit delays 110A-N, 116A-N. A large number of unit delays 110A-N, 116A-N is desirable to provide the SMD 100 with better resolution in generating the forward and backward delays FD, BD, which hereinafter will collectively be referred to as a variable delay VD (i.e., VD=FD+BD). The resolution of the SMD 100 is the smallest increment of delay that may be added and subtracted from the variable delay VD, which equals twice the unit delay UD of the unit delays 110A-N, 116A-N in the SMD 100. Better resolution means the CLK and CLKSYNC signals will be properly synchronized, as will be appreciated by those skilled in the art. In addition, the forward and backward delay lines 108, 114 must be able to collectively provide a maximum variable delay VD corresponding to the CLK signal having the lowest frequency in the frequency range over which the SMD 100 is designed to operate. This is true because the forward and backward delay lines 108, 114 must each provide a delay of Nxc3x97TCKxe2x88x92(D1+D2), which will have its largest value when the period TCK of the CLK signal is greatest, which occurs at the lowest frequency of the CLK signal.
Taken together, the desired resolution and maximum variable delay VD of the SMD 100 can result in the delay lines 108, 114 consisting of a large number of individual delay stages 110A-N, 116A-N that consume a relatively large amount of space on a semiconductor substrate in which the SMD 100 and other components of the synchronous memory device are formed. Moreover, such a large number of individual delay stages 110A-N, 116A-N can result in significant power consumption by the SMD 100, which may be undesirable, particularly in applications where the synchronous memory device is contained in a portable battery-powered device.
There is a need for an SMD having good resolution that occupies less space on a semiconductor substrate and consumes less power.
According to one aspect of the present invention, a synchronous mirror delay includes a ring oscillator that generates a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. A model delay line receives an input clock signal and generates a model delayed clock signal in response to the input clock signal. The model delayed clock signal has a model delay relative to the input clock signal. A coarse delay circuit generates a coarse delay count responsive to the oscillator, input, and model delayed clock signals, and also activates a coarse delay enable signal responsive to the delay count being equal to a reference count value. A fine delay circuit latches the tap clock signals responsive to the input clock signal and develops a fine delay from the latched tap clock signals. The fine delay circuit activates a fine delay enable signal in response to the coarse delay enable signal, the fine delay enable signal having the fine delay relative to the coarse delay enable signal. An output circuit is coupled to the coarse and fine delay circuits and generates a delayed clock signal responsive to the coarse and fine delay enable signals going active.